,,preliminary ,,specifications --- ,,programmed ,,data ,,processor ,,model ,,three 7,,pdp-#c7 --- ,october1 #aifj ,digital ,equipment ,corporation ,maynard1 ,massachusetts ,,table ,,of ,,contents ,,introduction #a ,general ,description #a ,system ,block ,diagram #a ,electrical ,description #d ,mechanical ,description #d ,environmental ,requirements #e ,,central ,,processor #f ,operating ,speeds #f ,instruction ,format #f ,number ,system #g ,indexing #h ,indirect ,addressing #h ,instruction ,list #i ,manual ,controls #bj ,,storage #bb ,,standard ,,input-,,output #bc ,paper ,tape ,reader #bc ,paper ,tape ,punch #bd ,typewriter #bd ,,optional ,,input-,,output #bf ,sequence ,break ,system #bf ,high ,speed ,in-,out ,channel #bf ,magnetic ,tape #bg ,,crt ,display #cc ,real ,time ,clock #cc ,line ,printer #cd ,,utility ,,programs #ce ,,frap ,system #ce ,,decal ,system #ce ,floating ,point ,subroutines #cf ,maintenance ,routines #cg ,miscellaneous ,routines #cg ,,introduction ,,general ,,description ,the ,,dec ,programmed ,data ,processor ,model ,three 7,,pdp-#c7 is a high performance1 large scale digital computer featuring reliability in operation together with economy in initial cost1 maintenance and use4 ,this combination is achieved by the use of very fast1 reliable1 solid state circuits coupled with system design restraint4 ,the simplicity of the system design excludes many marginal or superfluous features and thus their attendant cost and maintenance problems4 ,the average internal instruction execution rate is about #ajj1jjj operations per second with a peak rate of #bjj1jjj operations per second4 ,this speed1 together with its economy and reliability1 recommends ,,pdp-#c as an excellent instrument for complex real time control applications and as the center of a modern computing facility4 ,,pdp-#c is a stored program1 general purpose digital computer4 ,it is a single address1 single instruction machine operating in parallel on #cf bit numbers4 ,it features multiple step indirect addressing and indexing of addresses4 ,the main memory makes #eaa registers available as index registers4 ,the main storage is coincident current magnetic core modules of #djif words each4 ,the computer has a built-in facility to address #h modules and can be expanded to drive #fd modules4 ,the memory has a cycle time of five microseconds4 ,,system ,,block ,,diagram ,the flow of information between the various registers of ,,pdp-#c is shown in the ,system ,block ,diagram 7,fig4 #a74 ,there are four registers of #cf bit length4 ,their functions are described below4 ,memory ,buffer ,the ,memory ,buffer is the central switching register4 ,the word coming from or going to memory is retained in this register4 ,in arithmetic operations it holds the addend1 subtrahend1 multiplicand1 or divisor4 ,the left #f bits of this register communicate with the ,instruction ,register4 ,the address portion of the ,memory ,buffer ,register communicates with the ,index ,adder1 the ,memory ,address ,register1 and the ,program ,counter4 ,in certain instructions1 the address portion of the control word does not refer to memory but specifies variations of an instruction1 thus1 the address portion of the ,memory ,buffer is connected to the ,control ,element4 ,accumulator ,the ,accumulator is the main register of the ,arithmetic ,element4 ,sums and differences are formed in the ,accumulator4 ,at the completion of multiplication it holds the high order digits of the product4 ,in division it initially contains the high order digits of the dividend and is left with the remainder4 ,the logical functions ,,and1 inclusive ,,or1 and exclusive ,,or1 are formed in the ,accumulator4 ,carry ,storage ,register ,the ,carry ,storage ,register facilitates high-speed multiply and is properly part of the ,accumulator4 ,in-,out ,register ,the ,in-,out ,register is the main path of communication with external equipment4 ,it is also part of the ,arithmetic ,element4 ,in multiplication it ends with the low order digits of the product4 ,in division it starts with the low order parts of the dividend and ends with the quotient4 ,the ,in-,out ,register has a full set of shifting properties1 7arithmetic and logical74 99 99 99 99 99 ,there are three registers of #ae bit length which deal exclusively with addresses4 ,the design allows for expansion to #ah bits4 ,these registers are3 ,memory ,addressing ,the ,memory ,address ,register holds the number of the memory location that is currently being interrogated4 ,it receives this number from the ,program ,counter1 the ,index ,adder or the ,memory ,buffer4 ,program ,counter ,the ,program ,counter holds the memory location of the next instruction to be executed4 ,index ,adder ,the ,index ,adder is a #ae bit ring accumulator4 ,the sum of an instruction base address1 ,y1 and the contents of an index register1 ,c7x71 are formed in this register4 ,this register holds the previous content of the ,program ,counter in the jump and save ,program ,counter1 jps1 instruction4 ,the ,index ,adder also serves as the step counter in shift1 multiply1 and divide4 99 99 99 99 99 ,the ,control ,element contains two six bit registers and several miscellaneous flip-flops4 ,the latter deal with indexing1 indirect addressing1 memory control1 etc4 ,the six bit registers are3 ,instruction ,register ,the ,instruction ,register receives the first six bits of the ,memory ,buffer ,register during the cycle which obtains the instruction from memory 7cycle zero74 ,this information is the primary input to the ,control ,element4 ,program ,flags ,the six ,program ,flags act as convenient program switches4 ,they are used to indicate separate states of a program4 ,the program can set1 clear1 or sense the individual flip-flops4 ,the program can also sense or make the state ,all ,flags ,,zero4 ,they can also be used to synchronize various input devices which occur at random times 7see ,input-,output1 ,typewriter ,input74 99 99 99 99 99 ,three toggle switch registers are connected to the ,central ,processor 7see ,manual ,controls74 ,test ,address ,the fifteen ,test ,address ,switches are used to indicate start points and to select memory registers for manual examination or change4 ,test ,word ,the thirty-six ,test ,word ,switches indicate a new number for manual deposit into memory4 ,they may also be used for insertion of constants while a program is operating by means of the operate instruction4 ,sense ,switches ,the six ,sense ,switches allow the operator to manually select program options or cause a jump to another program in memory4 ,the program can sense individual switches or the state ,all ,switches ,,zero4 ,,electrical ,,description ,the ,,pdp-#c circuitry is the static type using saturating transistor flip-flops and1 for the most part1 transistor switch elements4 ,the primary active elements are ,micro-,alloy and ,micro-,alloy-,diffused transistors4 ,the flip-flops have built-in delay so that a logic net may be sampled and changed simultaneously4 ,machine timing is performed by a delay line chain4 ,auxiliary delay line chains time the step counter instructions 7multiply1 divide1 etc474 ,the machine is thus internally synchronous with step counter instructions being asynchronous4 ,the machine is asynchronous for in-out operations1 that is1 the completion of an in-out operation initiates the following instruction4 ,,mechanical ,,description ,the ,,pdp-#c consists of two mechanical assemblies1 the ,console and the ,equipment ,frame4 ,fig4 #c is a photograph of ,,pdp-#a which is an #ah bit version of ,,pdp-#c4 ,console ,the ,console is a desk approximately seven feet long4 ,it contains the controls and indicators necessary for operation and maintenance of the machine4 ,a cable connects the ,console to the ,equipment ,frame4 ,equipment ,frame ,the ,equipment ,frame is approximately six feet high and two feet deep4 ,the length is a function of the amount of optional features included4 ,the ,central ,processor requires a length of five and one half feet4 ,the power cabinet is twenty-two inches long4 ,a memory cabinet is thirty-two inches long and will hold three memory modules 7#ab1bhh words per cabinet74 ,memory cabinets may be added at any time4 ,magnetic tape units require twenty-two inches per transport4 ,a tape unit cabinet may be connected as an extension of the ,equipment ,frame or may be a free-standing frame4 ,,environmental ,,requirements ,the ,,pdp-#c requires no special room preparation4 ,the computer will operate properly over the normal range of room temperature4 ,the ,central ,processor and memory together require thirty amperes of #aaj volts single phase #fj cycle ac4 ,each inactive tape transport requires two amperes and the one active transport requires #aj amperes4 ,,central ,,processor ,the ,central ,processor of ,,pdp-#c contains the ,control ,element1 the ,memory ,buffer ,register1 the ,arithmetic ,element1 and the ,memory ,addressing ,element4 ,the ,control ,element governs the complete operation of the computer including memory timing1 instruction performance1 and the initiation of input-output commands4 ,the ,arithmetic ,element1 which includes the ,accumulator1 the ,in-,out ,register1 and the ,carry ,storage ,register1 performs the arithmetic operations4 ,the ,memory ,addressing ,element which includes the ,index ,adder1 the ,program ,counter1 and the ,memory ,address ,register1 performs address bookkeeping and modification4 ,,operating ,,speeds ,operating times of ,,pdp-#c instructions are normally multiples of the memory cycle of #e microseconds4 ,two cycle instructions refer twice to memory and thus require #aj microseconds for completion4 ,examples of this are add1 subtract1 deposit1 load1 etc4 ,one cycle instructions do not refer to memory and require #e microseconds4 ,examples of the latter are the jump instructions1 the skip instructions1 and the operate group4 ,the operating times of variable cycle instructions depend upon the instruction4 ,for example1 the operating time for a shift or rotate instruction is #e #j4b,n microseconds1 where ,n is the number of shifts performed4 ,the operating times for multiply and divide are functions of the number of ones in the multiplier and in the quotient1 respectively4 ,maximum time for multiply is #be microseconds4 ,this includes the time necessary to get the multiply instruction from memory4 ,divide takes #ij microseconds maximum4 ,in-,out ,transfer instructions that do not include the optional wait function require #e microseconds4 ,if the in-out device requires a wait time for completion1 the operating time depends upon the device being used4 ,if an instruction includes reference to an index register1 an additional #e microseconds is required4 ,each step of indirect addressing also requires an additional #e microseconds4 ,,instruction ,,format ,the instructions for ,,pdp-#c may be divided into three classes3 #a4 ,indexable memory instructions #b4 ,non-indexable memory instructions #c4 ,non-memory instructions4 ,the layout of the instruction word is shown in ,fig4 #b4 ,the octal digits #j and #a define the instruction code1 thus1 there are #fd possible instruction codes1 not all of which are used4 ,the first bit of octal digit #b is the indirect address bit4 ,if this bit is a ,,one1 indirect addressing occurs4 ,the index address1 ,x1 is in octal digits #c1 #d1 and #e4 ,these digits address an index register for memory-type instructions4 ,if these digits are all ,,zero1 indexing will not take place4 ,in main memory1 #eaa of the registers can be used as automatic index registers4 ,the instruction base address1 ,y1 is in octal digits #g through #aa4 ,these digits are sufficient to address #cb1gfh words of memory4 ,octal digit #f is reserved for further memory expansion4 ,space is available in the equipment frame for this expansion1 should it prove desirable4 ,in those instructions which do not refer to memory1 the memory address digits1 ,y1 and in some cases the index address digits also1 are used to specify the variations in any group of instructions4 ,an example of this is in the shift and rotate instructions in which the memory address digits determine the number of shifts4 ,,number ,,system ,the ,,pdp-#c is a fixed point machine using binary arithmetic4 ,negative numbers are represented as the #a's complement of the positive numbers4 ,bit #j is the sign bit which is ,,zero for positive numbers4 ,bits #a to #ce are magnitude bits with bit #a being the most significant and bit #ce being the least significant4 ,the actual position of the binary point may be arbitrarily assigned to best suit the problem in hand4 ,two common conventions in the placement of the binary point are3 #a4 ,the binary point is to the right of the least significant digit1 thus1 numbers represent integers4 #b4 ,the binary point is to the right of the sign digit1 thus the numbers represent a fraction which lies between #a4 ,the conversion of decimal numbers into the binary system for use by the machine may be performed automatically by subroutines4 ,similarly the output conversion of binary numbers into decimals is done by subroutine4 ,operations for floating point numbers are handled by programming4 ,the utility program system provides for automatic insertion of the routines required to perform floating point operations and number base conversion 7see ,utility ,programs74 ,,indexing ,in ,,pdp-#c1 #eaa registers of the main magnetic core memory are available for use as automatic index registers4 ,their addresses are specified by octal digits #c to #e of the instruction word4 ,these registers are memory locations #jja-ggg 7octal74 ,address #jjj specifies that no index register is to be used with the instructions4 ,the contents of octal digits #g through #aa of the selected index register are added to the unmodified address 7octal digits #g through #aa of the instruction74 ,this sum is used to locate the operand4 ,the addition is done in the ,index ,adder which is a #ae bit #a's complement adder4 ,the contents of the ,accumulator and the ,in-,out ,register are unaffected by the indexing process4 ,an instruction which has used indexing is retained in memory with its original address unmodified4 ,memory registers #a-ggg 7octal7 are available for use as normal memory registers if they are not being used as index registers4 ,the left half of these registers is available for the storage of constants1 tables1 etc41 when octal digits #g through #aa act as index registers4 ,three special instructions snx1 spx and lir1 are available to facilitate resetting1 advancing1 and sampling of the index registers4 ,since the index registers are normal memory registers1 their contents can also be manipulated by the standard computer instructions4 ,,indirect ,,addressing ,an instruction which is to use an indirect address will have a ,,one in bit six of the instruction word4 ,the original address1 ,y1 of the instruction will not be used to locate the operand of the instruction1 as is the normal case4 ,instead1 it is used to locate a memory register whose contents in octal digits #g through #aa will be used as the address of the original instruction4 ,this new address is known as the indirect address for the instruction and will be used to locate the operand4 ,if the memory register containing the indirect address also has a #a in bit six1 the indirect addressing procedure is repeated again and a third address is located4 ,there is no limit to the number of times this process can be repeated4 ,index registers may be used in conjunction with indirect addressing4 ,in this case1 the address after being modified by the selected index register is used to locate the indirect address4 ,the indirect address can be acted on by an index register and deferred again if desired4 ,each use of an index register or an indirect address extends the operating time of the original instruction by #e microseconds4 ,,instruction ,,list ,this list includes the title of the instruction1 the normal execution time of the instruction1 i4e41 the time with no indexing and no deferring1 the mnemonic code of the instruction1 and the operation code number4 ,the notation used requires the following definitions4 ,the contents of a register ,q are indicated as ,c7,q74 ,the address portion of the instruction is indicated by ,y4 ,the index register address of an instruction is indicated by x4 ,the effective address of an operand is indicated by ,z4 ,z may be equal to ,y or it may be ,y as modified by deferring or by indexing4 ,indexable ,memory ,instructions ,arithmetic ,instructions ,add 7#aj usec47 add x ,y ,operation ,code #dj ,the new ,c7,,ac7 are the sum of ,c7,z7 and the original ,c7,,ac74 ,the ,c7,z7 are unchanged4 ,the addition is performed with #a's complement arithmetic4 ,if the sum exceeds the capacity of the ,accumulator ,register1 the overflow flip-flop will be set 7see ,skip ,group instructions74 ,subtract 7#aj usec47 sub x ,y ,operation ,code #db ,the new ,c7,,ac7 are the original ,c7,,ac7 minus the ,c7,z74 ,the ,c7,z7 are unchanged4 ,the subtraction is performed using #a's complement arithmetic4 ,if the difference exceeds the capacity of the ,accumulator1 the overflow flip-flop will be set 7see ,skip ,group instructions74 ,multiply 7approximately #be usec47 mul x ,y ,operation ,code #ed ,the ,c7,,ac7 are multiplied by the ,c7,z74 ,the most significant digits of the product are left in the ,accumulator and the least significant digits in the ,in-,out ,register4 ,the previous ,c7,,ac7 are lost4 ,divide 7approximately #ij usec47 div x ,y ,operation ,code #ef ,the ,accumulator and the ,in-,out ,register together form a #gj bit dividend4 ,the high order part of the dividend is in the ,accumulator4 ,the low order part of the dividend is in the ,in-,out ,register4 ,the divisor is 7,z74 ,upon completion of the division1 the quotient is in the ,in-,out ,register4 ,the remainder is in the ,accumulator4 ,the sign of the remainder is the same as the sign of the dividend4 ,if the dividend is larger than ,c7,z71 the overflow flip-flop will be set and the division will not take place4 ,logical ,instructions ,logical ,,and 7#aj usec47 and x ,y ,operation ,code #jb ,the bits of ,c7,z7 operate on the corresponding bits of the ,accumulator to form the logical ,,and4 ,the result is left in the ,accumulator4 ,the ,c7,z7 are unaffected by this instruction4 ,logical ,,and ,function ,table ,,ac ,bit ,c7,z7 ,bit ,result #j #j #j #j #a #j #a #j #j #a #a #a ,exclusive ,,or 7#aj usec47 xor x ,y ,operation ,code #jf ,the bits of ,c7,z7 operate on the corresponding bits of the ,accumulator to form the exclusive ,,or4 ,the result is left in the ,accumulator4 ,the ,c7,z7 are unaffected by this order4 ,exclusive ,,or ,table ,,ac ,bit ,c7,z7 ,bit ,result #j #j #j #j #a #a #a #j #a #a #a #j ,inclusive ,,or 7#aj usec47 ior x ,y ,operation ,code #jd ,the bits of ,c7,z7 operate on the corresponding bits of the ,accumulator to form the inclusive ,,or4 ,the result is left in the ,accumulator4 ,the ,c7,z7 are unaffected by this order4 ,inclusive ,,or ,table ,,ac ,bit ,c7,z7 ,bit ,result #j #j #j #j #a #a #a #j #a #a #a #a ,general ,instructions ,load ,accumulator 7#aj usec47 lac x ,y ,operation ,code #bj ,the ,c7,z7 are placed in the ,accumulator4 ,the ,c7,z7 are unchanged4 ,the original ,c7,z7 are lost4 ,deposit ,accumulator 7#aj usec47 dac x ,y ,operation ,code #bd ,the ,c7,,ac7 replace the ,c7,z7 in the memory4 ,the ,c7,,ac7 are left unchanged by this instruction4 ,the original ,c7,z7 are lost4 ,deposit ,address ,part 7#aj usec47 dap x ,y ,operation ,code #bf ,octal digits #f through #aa of the ,accumulator replace the corresponding digits of memory register ,z4 ,c7,,ac7 are unchanged as are the contents of octal digits #j through #e of ,z4 ,the original contents of octal digits #f through #aa of ,z are lost4 ,deposit ,instruction ,part 7#aj usec47 dip x ,y ,operation ,code #cj ,octal digits #j through #e of the ,accumulator replace the corresponding digits of memory register ,z4 ,the ,accumulator is unchanged as are digits #f through #aa of ,z4 ,the original contents of octal digits #j through #e of ,z are lost4 ,load ,in-,out ,register 7#aj usec47 lio x ,y ,operation ,code #bb ,the ,c7,z7 are placed in the ,in-,out ,register4 ,c7,z7 are unchanged4 ,the original ,c7,,io7 are lost4 ,deposit ,in-,out ,register 7#aj usec47 dio x ,y ,operation ,code #cb ,the ,c7,,io7 replace the ,c7,z7 in memory4 ,the ,c7,,io7 are unaffected by this instruction4 ,the original ,c7,z7 are lost4 ,jump 7#e usec47 jmp x ,y ,operation ,code #fj ,the ,program ,counter is reset to address ,z4 ,the next instruction that will be executed will be taken from memory register ,z4 ,the original contents of the ,program ,counter are lost4 ,jump and ,save ,program ,counter 7#e usec47 jsp x ,y ,operation ,code #fb ,the contents of the ,program ,counter are transferred to the ,index ,adder4 ,when the transfer takes place1 the ,program ,counter holds the address of the instruction following the jsp4 ,the ,program ,counter is then reset to address ,z4 ,the next instruction that will be executed will be taken from memory register ,z4 ,skip if ,accumulator and ,z differ 7#aj usec47 sad x ,y ,operation ,code #ej ,the ,c7,z7 are compared with the ,c7,,ac74 ,if the two numbers are different1 the ,program ,counter is indexed one extra position and the next instruction in the sequence is skipped4 ,the ,c7,,ac7 and the ,c7,z7 are unaffected by this operation4 ,skip if ,accumulator and ,z are the same 7#aj usec47 sas x ,y ,operation ,code #eb ,the ,c7,z7 are compared with ,c7,,ac74 ,if the two numbers are identical1 the ,program ,counter is indexed one extra position and the next instruction in the sequence is skipped4 ,the ,c7,,ac7 and ,c7,z7 are unaffected by this operation4 ,non-,indexable ,memory ,instructions ,these instructions have the same word format as the indexable instructions4 ,since they operate on the index register location1 x1 they cannot be indexed4 ,skip on ,negative index 7#aj usec47 snx x ,y ,operation ,code #df ,the number in octal digits #g through #aa of the instruction word is added to the ,c7x74 ,this addition is done in the #ae bit ,index ,adder using #a's complement arithmetic4 ,if1 after the addition1 the sum is negative1 the ,program ,counter is advanced one extra position and the next instruction in the sequence is skipped4 ,the contents of octal digits #j-e of the index register location are unaffected by this instruction4 ,skip on ,positive index 7#aj usec47 spx x ,y ,operation ,code #dd ,the number in octal digits #g through #aa of the instruction word is added to the ,c7x74 ,this addition is done in the #ae bit ,index ,adder using #a's complement arithmetic4 ,if1 after the addition1 the sum is positive1 the ,program ,counter is advanced one extra position and the next instruction in the sequence is skipped4 ,the contents of octal digits #j-e of the index register location are unaffected by this instruction4 ,load ,index ,register 7#aj usec47 lir x ,y ,operation ,code #ad ,the octal digits #g through #aa 7,y7 of the instruction will replace the corresponding digits of the memory register specified by x4 ,octal digit #f of the memory register will be left clear4 ,digits #j-e of the memory register are unchanged4 ,deposit ,index ,adder 7#aj usec47 dia x ,y ,operation ,code #af ,the ,c7,,ia7 replace the octal digits #g through #aa of memory location ,y4 ,octal digit #f of ,y is cleared4 ,digits #j through #e of ,y are left unchanged4 ,the x portion of the instruction is ignored4 ,non-,memory ,instructions ,rotate and ,shift ,group ,this group of instructions will rotate or shift the ,accumulator and_/or the ,in-,out ,register4 ,when the two registers operate combined1 the ,in-,out ,register is considered to be a #cf bit magnitude extension of the right end of the ,accumulator4 ,rotate is a non-arithmetic cyclic shift4 ,that is1 the two ends of the register are logically tied together and information is rotated as though the register were a ring4 ,shift is an arithmetic operation and is in effect multiplication of the number in the register by #b,n1 where ,n is the number of shifts4 ,shift or rotate instructions involving more than #cc steps can be used for simulating time delays4 #cf rotate steps of the ,accumulator will return all information to its original position4 ,rotate ,accumulator ,right 7#ac usec4 maximum for #cf shifts7 rar ,n ,operation ,code #fga ,this instruction will rotate the bits of the ,accumulator right ,n positions1 where ,n is octal digits #g-aa of the instructions word4 ,rotate ,accumulator ,left 7#ac usec4 maximum for #cf shifts7 ral ,n ,operation ,code #ffa ,this instruction will rotate the bits of the ,accumulator left ,n ,positions1 where ,n is octal digits #g-aa of the instruction word4 ,shift ,accumulator ,right 7#ac usec4 maximum for #cf shifts7 sar ,n ,operation ,code #fge ,this instruction will shift the contents of the ,accumulator right ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,shift ,accumulator ,left 7#ac usec4 maximum for #cf shifts7 sal ,n ,operation ,code #ffe ,this instruction will shift the contents of the ,accumulator left ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,rotate ,in-,out ,register ,right 7#ac usec4 maximum for #cf shifts7 rir ,n ,operation ,code #fgb ,this instruction will rotate the bits of the ,in-,out ,register right ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,rotate ,in-,out ,register ,left 7#ac usec4 maximum for #cf shifts7 ril ,n ,operation ,code #ffb ,this instruction will rotate the bits of the ,in-,out ,register left ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,shift ,in-,out ,register ,right 7#ac usec4 maximum for #cf shifts7 sir ,n ,operation ,code #fgf ,this instruction will shift the contents of the ,in-,out ,register right ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,shift ,in-,out ,register ,left 7#ac usec4 maximum for #cf shifts7 sil ,n ,operation ,code #fff ,this instruction will shift the contents of the ,in-,out ,register left ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,rotate ,,ac and ,,io ,right 7#ac usec4 maximum for #cf shifts7 rcr ,n ,operation ,code #fgc ,this instruction will rotate the bits of the combined register right in a single ring ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,rotate ,,ac and ,,io ,left 7#ac usec4 maximum for #cf shifts7 rcl ,n ,operation ,code #ffc ,this instruction will rotate the bits of the combined register left in a single ring ,n position1 where ,n is octal digits #g-aa of the instruction word4 ,shift ,,ac and ,,io ,right 7#ac usec4 maximum for #cf shifts7 scr ,n ,operation ,code #fgg ,this instruction will shift the contents of the combined register right ,n positions1 where ,n is octal digits #g-aa of the instruction word4 ,shift ,,ac and ,,io ,left 7#ac usec4 maximum for #cf shifts7 scl ,n ,operation ,code #ffg ,this instruction will shift the contents of the combined registers left ,n positions1 where ,n is octal digits #g-aa of the instruction word4 99 99 99 99 99 ,skip ,group 7#e usec47 skp ,y ,operation ,code #fd ,this group of instructions senses the state of various flip-flops and switches in the machine4 ,it does not require any reference to memory4 ,the address portion of the instruction selects the particular function to be sensed4 ,all members of this group have the same operation code4 ,skip on ,,zero ,accumulator 7#e usec47 sza ,address #ajj ,if the ,accumulator is equal to plus ,,zero 7all bits are ,,zero7 the ,program ,counter is advanced one extra position and the next instruction in the sequence is skipped4 ,skip on ,plus ,accumulator 7#e usec47 spa ,address #bjj ,if the sign bit of the ,accumulator is ,,zero1 the ,program ,counter is advanced one extra position and the next instruction in the sequence is skipped4 ,skip on ,minus ,accumulator 7#e usec47 sma ,address #djj ,if the sign bit of the ,accumulator is ,,one1 the ,program ,counter is advanced one extra position and the next instruction in the sequence is skipped4 ,skip on ,,zero ,overflow 7#e usec47 szo ,address #ajjj ,if the overflow flip-flop is a ,,zero the ,program ,counter is advanced one extra position and the next instruction in the sequence will be skipped4 ,the overflow flip-flop is cleared by this instruction4 ,this flip-flop is set by addition1 subtraction1 or division that exceeds the capacity of the ,accumulator4 ,the overflow flip-flop is not cleared by arithmetic operations which do not cause an overflow4 ,thus1 a whole series of arithmetic operations may be checked for correctness by a single szo4 ,the overflow flip-flop is cleared by the ,start ,switch4 ,skip on ,plus ,in-,out ,register 7#e usec47 spi ,address #bjjj ,if the sign digit of the ,in-,out ,register is ,,zero the ,program ,counter is indexed one extra position and the next instruction in the sequence is skipped4 ,skip on ,,zero ,switch 7#e usec47 szs ,addresses #aj1 #bj1 444 #gj ,if the selected ,sense ,switch is ,,zero1 the ,program ,counter is advanced one extra position and the next instruction in the sequence will be skipped4 ,address #aj senses the position of ,sense ,switch #a1 ,address #bj ,switch #b1 etc4 ,address #gj senses all the switches4 ,if #gj is selected all #f switches must be ,,zero to cause the skip to occur4 ,skip on ,,zero ,program ,flag 7#e usec47 szf ,addresses #j to #g inclusive ,if the selected program flag is a ,,zero1 the ,program ,counter is advanced one extra position and the next instruction in the sequence will be skipped4 ,address #j is no selection4 ,address #a selects program flag one1 etc4 ,address #g selects all programs flags4 ,all flags must be ,,zero to cause the skip4 ,the instructions in the ,one ,cycle ,skip group may be combined to form the inclusive ,,or of the separate skips4 ,thus1 if address #cjjj is selected1 the skip would occur if the overflow flip-flop equals ,,zero or if the ,in-,out ,register is positive4 ,the combined instruction would still take #e microseconds4 99 99 99 99 99 ,operate ,group 7#e usec47 opr ,y ,operation ,code #gf ,this instruction group performs miscellaneous operations on various ,central ,processor ,registers4 ,the address portion of the instruction specifies the action to be performed4 ,clear ,in-,out ,register 7#e usec47 cli ,address equal #djjj ,this instruction clears the ,in-,out ,register4 ,load ,accumulator from ,test ,word 7#e usec47 lat ,address #bjjj ,this instruction forms the inclusive ,,or of the ,c7,,ac7 and the contents of the ,test ,word4 ,this instruction is usually combined with address #bjj 7clear ,accumulator71 so that ,c7,,ac7 will equal the contents of the ,test ,word ,switches4 ,complement ,accumulator 7#e usec47 cma ,address #ajjj ,this instruction complements 7makes negative7 the contents of the ,accumulator4 ,halt hlt ,address #djj ,this instruction stops the computer4 ,clear ,accumulator 7#e usec47 cla ,address #bjj ,this instruction clears 7sets equal to plus #j7 the contents of the ,accumulator4 ,clear ,selected ,program ,flag 7#e usec47 clf ,address #ja to #jg inclusive ,the selected program flag will be cleared4 ,address #jj selects no program flag1 #ja clears program flag #a1 #jb clears program flag #b1 etc4 ,address #jg clears all program flags4 ,set ,selected ,program ,flag 7#e usec47 stf ,address #aa to #ag inclusive 99 99 99 99 99 ,in-,out ,transfer ,group 7#e usec4 without in-out wait7 iot x ,y ,operation ,code #gb ,the variations within this group of instructions perform all the in-out control and information transfer functions4 ,if bit six 7normally the ,indirect ,address bit7 is a ,,one1 the computer will halt and wait for the completion pulse from the device activated4 ,when this device delivers its completion1 the computer will resume operation of the instruction sequence4 ,an incidental fact which may be of importance in certain scientific or real time control applications is that the time origin of operations following an in-out completion pulse is identical with the time of that pulse4 ,most in-out operations require a known minimum time before completion4 ,this time may be utilized for programming4 ,the appropriate ,in-,out ,transfer is given with no in-out wait 7bit six a ,,zero74 ,the instruction sequence then continues4 ,this sequence must include an iot instruction which performs nothing but the in-out wait4 ,this last instruction must occur before the safe minimum time4 ,a table of minimum times for all in-out devices is delivered with the computer4 ,it lists minimum time before completion pulse and minimum ,in-,out ,register free time4 ,the details of the ,in-,out ,transfer variations are listed under ,input-,output4 ,the mnemonic codes and addresses for the standard equipment are3 ,read ,paper ,tape ,alphanumeric ,mode rpa ,address #a ,read ,paper ,tape ,binary ,mode rpb ,address #b ,typewriter ,output tyo ,address #c ,typewriter ,input tyi ,address #d ,punch ,paper ,tape ,alphanumeric ,mode ppa ,address #e ,punch ,paper ,tape ,binary ,mode ppb ,address #f ,,manual ,,controls ,the ,console of ,,pdp-#c has controls and indicators for the use of the operator4 ,fig4 #d is a close-up of the control panel of ,,pdp-#a1 the #ah bit version of ,,pdp-#c4 ,all computer flip-flops have indicator lights on the ,console4 ,these indicators are primarily for use when the machine has stopped or when the machine is being operated one step at a time4 ,while the machine is running1 the brightness of an indicator bears some relationship to the relative duty factor of that particular flip-flop4 ,three registers of toggle switches are available on the ,console4 ,these are the ,test ,address 7#ae bits71 the ,test ,word 7#cf bits71 and the ,sense ,switches 7#f bits74 ,the first two are used in conjunction with the operating push buttons4 ,the ,sense ,switches are present for manual intervention4 ,the use of these switches is determined by the program 7see ,system ,block ,diagram and ,skip ,group ,instructions74 ,operating ,push ,buttons ,start - ,when this switch is operated1 the computer will start4 ,the first instruction comes from the memory location indicated in the ,test ,address ,switches4 ,stop - ,the computer will come to a halt at the completion of the current memory cycle4 ,continue - ,the computer will resume operation starting at the state indicated by the lights4 ,examine - ,the contents of the memory register indicated in the ,test ,address will be displayed in the ,accumulator and the ,memory ,buffer lights4 ,deposit - ,the word selected by the ,test ,word ,switches will be put in the memory location indicated by the ,test ,address ,switches4 ,read-,in - ,when this switch is operated1 the photoelectric paper tape reader will start operating in the ,read-,in mode4 7see ,input-,output74 ,in addition to the operating push buttons1 there are several separate toggle switches4 ,single ,cycle ,switch - ,when the ,single ,cycle ,switch is on1 the computer will halt at the completion of each memory cycle4 ,this switch is particularly useful in debugging programs4 ,repeated operation of the ,continue ,switch button will step the program one cycle at a time4 ,the programmer is thus able to examine the machine states at each step4 ,test ,switch - ,when the ,test ,switch is on1 the computer will perform the instruction indicated in the ,test ,address location4 ,it will repeat this instruction either at the normal speed rate or at a single cycle rate if the ,single ,cycle ,switch is up4 ,this switch is primarily useful for maintenance purposes4 ,sense ,switches - ,there are six switches on the ,console which are present for manual intervention4 ,,storage ,the internal ,memory ,system for ,,pdp-#c consists of modules of #djif words of coincident current magnetic core storage4 ,each word has #cf bits4 ,the memory modules operate with a read-rewrite cycle time of #e microseconds4 ,the driving currents of the memory are automatically adjusted to compensate for normal room temperature variations4 ,each core memory module consists of the memory stack1 the required ,x and ,y switches1 the ,x and ,y current sources and sense amplifiers for that stack4 ,the ,memory ,address ,register1 the ,memory ,buffer ,register1 and the ,memory ,timing ,controls are considered to be part of the ,central ,processor4 ,the standard ,,pdp-#c ,memory ,address ,register configuration is built to allow up to #h modules of core memory 7#cb1gfh words74 ,there is a space in the addressing section of the machine to allow expansion of the addressing by a factor of eight for a total addressing capacity of #bfb1add memory registers4 ,the ,core ,memory may be supplemented by ,magnetic ,tape ,storage4 ,this is described under ,input-,output4 ,,standard ,,input-,,output ,the ,,pdp-#c is designed to accommodate a variety of input-output equipment4 ,standard input-output units include a ,paper ,tape ,reader1 ,paper ,tape ,punch and an ,electric ,typewriter4 ,a single instruction1 ,in-,out ,transfer 7see ,central ,processor71 performs all in-out operations through the #cf bit ,in-,out ,register4 ,the address portion of this instruction specifies the in-out function4 ,one bit of the instruction selects an in-out halt as required4 ,,paper ,,tape ,,reader ,the ,paper ,tape ,reader of the ,,pdp-#c is a photoelectric device capable of reading #cjj lines per second4 ,six lines form the standard #cf bit word when reading binary punched eight hole tape4 ,five1 six and seven hole tape may also be read4 ,the reader will operate in one of two basic modes or in a third special mode4 ,alphanumeric ,mode rpa iot #a ,in this mode1 one line of tape is read for each ,in-,out ,transfer4 ,all eight holes of the line are read4 ,the information is left in the right eight bits of the ,in-,out ,register1 the remainder of the register being left clear4 ,the standard ,,pdp alphanumeric paper tape code includes an odd parity bit which may be checked by the program4 ,tape of non-standard width would be read in this mode4 ,binary ,mode rpb iot #b ,for each ,in-,out ,transfer instruction1 six lines of paper tape are read and assembled in the ,in-,out ,register to form a full computer word4 ,for a line to be recognized in this mode1 the eighth hole must be punched2 i4e41 lines with no eighth hole will be skipped over4 ,the seventh hole is ignored4 ,the pattern of holes in the binary tape is arranged so as to be easily interpreted visually in terms of machine instruction4 ,read-,in ,mode ,this is a special mode activated by the ,read-,in ,switch on the ,console4 ,it provides a means of entering programs which neither rely on read-in programs in memory nor require a plug board4 ,pushing the ,read-,in ,switch starts the reader in the binary mode4 ,the first group of six lines and alternate succeeding groups of six lines are interpreted as ,read-,in mode instructions4 ,even-numbered groups of #f lines are data4 ,the ,read-,in mode instructions must be either deposit in-out 7dio ,y7 or jump 7jmp ,y74 ,if the instruction is dio ,y1 the next group of six binary lines will be stored in memory location ,y and the reader continues moving4 ,if the instruction is jmp ,y1 the ,read-,in mode is terminated and the computer will commence operation at the address of the jump instruction4 ,,paper ,,tape ,,punch ,the standard ,,pdp-#c ,paper ,tape ,punch has a nominal speed of #bj lines per second4 ,it can operate in either the alphanumeric mode or the binary mode4 ,alphanumeric ,mode ppa iot #e ,for each ,in-,out ,transfer instruction one line of tape is punched4 ,in-,out ,register bit #ce conditions hole #a4 ,bit #cd conditions hole #b1 etc4 ,bit #bh conditions hole #h4 ,binary ,mode ppb iot #f ,for each ,in-,out ,transfer instruction one line of tape is punched4 ,in-,out ,register bit five conditions hole #a4 ,bit four conditions hole #b1 etc4 ,bit zero conditions hole #f4 ,hole #g is left blank4 ,the #h hole is always punched in this mode4 ,,typewriter ,the ,typewriter will operate in the input mode or the output mode4 ,output ,mode tyo iot #c ,for each ,in-,out ,transfer instruction one character is typed4 ,the character is specified by the right six bits of the ,in-,out ,register4 ,input ,mode tyi iot #d ,this operation is completely asynchronous and is therefore handled differently than any of the preceding in-out operations4 ,when a ,typewriter key is struck1 ,program ,flag ,number ,one is set4 ,at the same time the code for the struck key is presented to gates connected to the right six bits of the ,in-,out ,register4 ,this information will remain at the gate for a relatively long time by virtue of the slow mechanical action4 ,a program designed to accept typed-in data would periodically check the status of ,program ,flag ,one4 ,if at any time ,program ,flag ,one is found to be set1 an ,in-,out ,transfer instruction with address four must be executed for information to be transferred4 ,this ,in-,out ,transfer normally should not use the optional in-out halt4 ,the information contained in the ,typewriter's coder is then read into the right six bits of the ,in-,out ,register4 ,,optional ,,input-,,output ,the ,,pdp-#c is designed to accommodate a variety of input-output equipment4 ,of particular interest is the ease with which new1 and perhaps unusual1 external equipment can be added to the machine4 ,optional in-out devices include ,cathode ,ray ,tube ,display1 ,magnetic ,tape1 ,real ,time ,clock1 ,line ,printer and ,analog to ,digital ,converters4 ,the method of operation of ,,pdp-#c with these optional devices is similar to the standard input-output equipment4 ,,sequence ,,break ,,system ,an optional in-out control is available for ,,pdp-#c4 ,this control1 termed the ,sequence ,break ,system1 allows concurrent operation of several in-out devices and the main sequence4 ,the system has1 nominally1 #af automatic interrupt channels arranged in a priority chain4 ,a break to a particular sequence may be initiated by the completion of an in-out device1 the program1 or an external signal4 ,if this sequence has priority1 the ,c7,,ac71 ,c7,,io71 ,c7,,pc71 and ,c7,,ia7 are stored in three fixed memory locations unique to that sequence4 ,since the ,c7,,pc7 and ,c7,,ia7 are eighteen bits each1 these two registers are stored in one memory location4 ,the next instruction is taken from a fourth location4 ,this instruction is usually a jump to a suitable routine4 ,the program is now operating in the new sequence4 ,this new sequence may be broken by a higher priority sequence4 ,a typical program loop for handling an in-out sequence would contain #c to #e instructions1 including the appropriate iot4 ,these are followed by load ,,ad and load ,,io from the fixed locations and a special indirect jump through the location of the previous ,c7,,pc74 ,this special jump also loads the ,,ia4 ,this last instruction terminates the sequence4 ,,high ,,speed ,,in-,,out ,,channel ,the device connected to an in-out channel communicates directly with memory through the ,memory ,buffer ,register4 ,at the completion of each machine instruction1 a check is made to see if the in-out channel has a word for1 or needs a word from1 the memory4 ,when necessary1 a memory cycle is taken to serve the channel4 ,the operation is initiated by an in-out command4 ,the in-out transfer command indicates the nature of the transfer4 ,the left half of the ,in-,out ,register must contain the starting address of the transfer1 and the right half must contain the number of words to be transferred4 ,if the ,sequence ,break ,system is connected1 the completion of the transfer will signal the proper sequence4 ,if no ,sequence ,break ,system is connected1 the completion of the in-out channel transfer sets a program flag4 ,,magnetic ,,tape ,the system consists of tape units connected to the ,,pdp-#c through a tape control 7,,tc74 ,this tape is read or written in ,,ibm #gbi;,i format4 ,two hundred characters1 each having #f bits plus a parity bit1 are written on each inch of tape and the tape moves at #ge inches_/sec4 ,the tape control has the job of connecting a specific unit to the ,,pdp-#c and is a switch4 ,it also has the function of controlling the format of information that is read or written on tape4 ,in-out class commands instruct ,,tc to the type of information transfer and select the tape unit4 ,another ,,iot command synchronizes the transfer of information through the ,,tc to the computer4 ,the ,,iot order to select the unit and function is decoded as follows3 #a7 ,three bits specify the function of ,,tc4 #b7 ,the remaining #f bits select the unit4 ,,iot ,motion ,commands for ,magnetic ,tape ,units ,,iot ,code ,abbreviation ,function #gc4444nn #fj mrb ,read a binary record4 #gc4444nn #fa mra ,read an alphanumeric 7,,bcd7 record4 #gc4444nn #fb mbb ,backspace a binary record4 #gc4444nn #fc mba ,backspace an alphanumeric record4 #gc4444nn #fd mwb ,write a binary record4 #gc4444nn #fe mwa ,write an alphanumeric record4 #gc4444nn #ff mlp ,move tape to lead point 7rewind74 ,where the octal digits1 nn1 specify the unit number4 ,the motion commands have the deferred bit1 thus1 the program halts4 ,if the ,,tc is free1 the command will be transferred to the tape control for action and the program restarts immediately4 ,if the tape control is currently busy with an instruction1 i4e41 it hasn't finished a previous command1 the motion command is held up until ,,tc is free to execute the new command4 ,the transfer of information from the computer to the ,,tc is accomplished with the pause and skip command1 ,,mps or ,,iot #gj4 ,this command has the deferred bit and halts a program until the ,,tc can handle the transfer4 ,on completion1 the transfer occurs and the program restarts4 ,this is used exclusively to synchronize the flow of information between a tape unit and the computer4 ,this command normally skips the following instruction4 ,if a flag is set in the ,,tc1 indicating incorrect information flow1 the skip does not take place4 ,the ,,tc contains a #cf bit buffer which holds a complete word while information is read or written4 ,when an ,,mps order is given and the unit is reading1 the ,,tc buffer is read into the ,,io4 ,the ,,mps order given during writing causes the ,,io to be transferred to the ,,tc buffer4 ,various conditions occurring in the ,,tc cause the no-skip condition1 when an ,,mps is given4 ,tape control flags are examined by the command1 examine and clear flags1 ,,mec or ,,iot #ga4 ,when ,,mec is given1 the flags are put into the ,,io for program interrogation1 and the flags cleared4 ,the flags are3 parity1 end of tape1 an end of record flag1 and reading-writing check4 ,the parity flag is set if the parity condition is not met while the tape is being read 7during ,,mwa1 ,,mwb1 ,,mra1 or ,,mrb74 ,the end of tape flag is set when the tape comes to the end of tape1 moving in either direction4 ,three conditions set the read-write check flag3 #a7 ,if ,,tc is inactive1 i4e41 no unit or function selected1 and an ,,mps instruction is given4 ,the ,,mps becomes a no-operation1 no-halt instruction4 #b7 ,when reading information and not emptying the ,,tc buffer1 by giving an ,,mps before more information arrives from tape4 #c7 ,a unit becomes unavailable during a normal sequence4 ,the end of record flag is set during reading or backspacing when the tape comes to an end of record gap4 ,writing a ,record of ,information ,information is written on the tape by giving a ,,mwb or ,,mwa command4 ,this sets a write binary or a write alphanumeric into the ,,tc and selects the unit4 ,a motion select command is executed immediately if the ,,tc is free1 otherwise1 the command waits until it can be executed4 ,normal programming can continue after the ,,mwa or ,,mwb is given for approximately #e milliseconds4 ,at this time1 an ,,mps order is given and the program pauses until information can be written4 ,when the ,,mps is restarted1 information is transferred to the ,,tc buffer from the ,,io4 ,if no flags have been set1 the following instruction is skipped4 ,three-quarter inches of blank tape is written by giving either the ,,mwa or ,,mwb order4 ,an end of file is written as follows3 #a7 ,four ,,mwa commands write three inches of blank tape4 #b7 ,then end of file character is written by giving the ,,mps order4 ,information is read and checked for correct parity while writing4 ,if too many program steps are given between the motion select command1 ,,mwa or ,,mwb and the first ,,mps1 the unit will deselect 7or disconnect74 ,the ,,mps is then a no-operation command4 ,writing ,program ,as an example1 a program to write k words in binary format from storage beginning in register ,a1 using tape unit number #jd1 is shown4 ,the following program is written in standard ,,frap language4 ,the program begins in register enterwrite4 enterwrite mec 1clear flags initially mwb #djj 1#gcjjjjjjdfd lir x_/-k#a 1initialize index register x b lio x_/ak-#a 1begin loop mps 1wait for ,,tc then write ,c7,z7 jmp c 1error spx x_/#a 1add #a to index register x jmp b 1return of loop jmp done 1record written c mec 1tape error ril #a spi jmp rwcstop 1read-write error or tape fault ril #a spi jmp b#c 1tape end hlt 1tape parity done 1resume programming ,reading ,information ,information is read by giving the ,,mra or ,,mrb order4 ,almost #aj ms4 is available after a read order is given before information actually enters the ,,tc buffer4 ,to read a record of unknown length1 the read order is first given4 ,the ,,mps order halts the program until six characters are assembled in the ,,tc information buffer4 ,the next instruction after the ,,mps1 a jump instruction1 transfers control from the loop when any flag is set4 ,the next instruction deposits the ,,io4 ,the record length is determined by not skipping after the ,,mps order on the setting of the end of record flag4 ,the read-write check flag or the end of record flag is then interrogated to see that the tape is actually at the end of record4 ,if a tape is not at the end of record1 then the tape is either at the end of the reel1 or a parity check has occurred4 ,reading ,program ,program to read j binary words into storage beginning in register d1 using tape unit #aj1 j is unknown4 ,the program begins in register enteread4 enteread mec 1clear flags initially mrb #ajjj 1#gcjjjjjjajfj dzm x 1put zero in memory location x e mps jmp outcheck dio x_/d 1store in location modified by x snx x_/#a 1add #a to ,c7x7 jmp e outcheck mec 1examine flags spi 1end of record8 jmp recordend 1yes hlt 1error recordend snx x_/#a 1to find value of j 1resume programming ,c7,,ia7 j ,forward ,spacing ,forward spacing is done by giving an ,,mrb or ,,mra order4 ,this moves the tape forward with the read-write head positioned at the end of the following record4 ,if n read orders are given1 the tape is spaced forward n records4 ,by giving the ,,mec order1 parity flags are examined to see that information on tape has been read correctly4 ,backspacing ,by giving an ,,mba or ,,mbb order the tape is moved backwards a record with the read-write heads positioned in the previous end of record gap4 ,the end of record flag is set when the tape has moved backwards a record4 ,rewinding ,rewinding is accomplished by giving the rewind order1 move tape to load point1 ,,mlp4 ,the rewind order starts a unit rewinding and does not tie up the ,,tc4 ,if a motion command is given which calls for a unit that is rewinding1 the command is executed1 but the action will not take place until the unit is available4 ,unit ,availability ,a unit is unavailable to the program under the following conditions3 #a4 ,unit is rewinding4 #b4 ,tape is improperly loaded4 #c4 ,cover door open4 #d4 ,unit overloaded4 #e4 ,unit under manual control4 #f4 ,power off4 ,a selected but unavailable unit holds up the ,,tc if a motion order is given for the unit4 ,the ,,tc will be held up until the unit is ready4 ,flag ,positions ,,io ,bit ,flag #j ,,eor - ,end of record #a ,,rwf - ,read-,write #b ,,eot - ,end of ,tape #c ,parity ,connection with ,high ,speed ,channel ,the high speed channel directs the tape control1 and word transfer1 just as a program would4 ,a unit is first started reading or writing4 ,the high speed channel is given the memory location of the information1 and the number of registers the words read or written will occupy4 ,the channel effects the information transfer4 ,thus1 a high speed channel connected to a tape control handles the programming for the unit word transfers4 ,completion of the block transfer is signified by either setting a program flag1 or entering the sequence break4 ,connection with ,sequence ,break ,system ,when the ,,tc is connected to the ,sequence ,break ,system1 the program is automatically interrupted each time an ,,mps command needs to be given4 ,programming is unaffected during reading and a record may be read with no flags set4 ,the ,,tc initiates breaks so that an ,,mps may be given in time4 ,similarly1 the break is initiated during writing each time an ,,mps needs to be given4 ,motion ,command ,summary ,time before ,time between ,time after ,end of ,flags that first ,,mps ,,mps's ,record to deselect may be set ,,mwa #c ms4 #djj us4 #aj ms4 ,,rwf 7if unit ,,mwb 7longer time is deselected causes deselection7 and ,,mps given1 or unit becomes unavailable71 ,parity1 ,,eot4 ,,mra #g ms4 #djj us4 #e ms4 ,,rwf1 7if ,,mrb 7longer time information misses information1 is missed1 or and unit becomes rwc set7 unavailable71 ,,eot1 ,,eor1 ,parity4 ,,mba - - #aj ms4 ,,rwf 7if unit ,,mbb becomes unavailable71 ,,eor1 ,,eot4 ,,cathode-,,ray-,,tube ,,display ,the ,,pdp-#c ,cathode ,ray ,tube ,display is useful for presentation of graphical or tabular information to the operator4 ,it uses a #af inch round tube with magnetic deflection4 ,for each ,in-,out transfer order1 one point is displayed at the position indicated by the ,in-,out ,register4 ,bits #j-i of the ,,io indicate the ,x coordinate of the position1 and bits #ah-bg indicate the ,y coordinate4 ,the display takes #fj microseconds4 ,an additional display option is a ,light ,pen4 ,by use of this device the computer is signaled that the operator is interested in the last point displayed4 ,thus the program can take appropriate action such as changing the display or shifting operation to another program4 ,a smaller display is available4 ,this display uses a five inch1 high resolution cathode ray tube4 ,the tube is equipped with a mounting bezel to accept a camera or photomultiplier device4 ,the operation of this display is similar to that of the #af inch1 except that #ab bits are decoded for each axis4 ,,real ,,time ,,clock ,a special input register may be connected to operate as a ,real ,time ,clock4 ,this is a counting register operated by a crystal controlled oscillator4 ,the clock can be reset to zero by manual operation4 ,a toggle switch interlock prevents an accidental reset4 ,the state of this counter may be read at any time by the appropriate ,in-,out ,transfer instruction4 ,,line ,,printer ,a #gb column ,anelex printer and control are available as an option for ,,pdp-#c4 ,the control contains a one line buffer4 ,this buffer is cleared by the completion of an order to space the paper one position 7psp74 ,the buffer is filled from the ,in-,out ,register by a succession of #ab load buffer orders 7plb74 ,the first plb will put the six characters represented by ,c7,,io7 in the leading 7left-hand7 column positions of the buffer4 ,after the buffer is loaded1 the order1 print 7pnt71 is given4 ,,utility ,,programs ,,frap-#c - ,the ,assembly ,program ,an assembler or compiler prepares a machine language tape suitable for direct interpretation by the computer from a program tape in operator language4 ,generally speaking1 one statement accepted by ,,frap produces one instruction for the machine4 ,a single statement written for the ,,pdp-#c compiler1 ,,decal-#c1 may cause several instructions to be written4 ,thus1 ,,frap causes a #a for #a mapping of instructions for statements while ,,decal may produce many instructions from one statement4 ,in addition to allowing program tapes to be prepared with off line equipment1 an assembly program has other functions4 ,normally1 the machine would require #cf bits or #ab octal digits to be written for each instruction used in the machine4 ,,frap allows mnemonic symbols to be used for the instructions4 ,these mnemonic symbols aid the programmer by representing the instruction in an easily remembered form4 ,in addition to allowing mnemonic symbols to represent the instructions1 variable length sequences of alphanumeric characters may be used to represent memory addresses in symbolic form4 ,the assembly program does the address bookkeeping for the programmer4 ,a short example of a ,,frap program is on ,page #bi4 ,since few characters limit or control the format of instructions written in ,,frap-#c language1 it is possible to write instructions in almost any format or style4 ,,frap-#c may also be used to prepare tapes for interpretive programming1 since arbitrary definitions for operation code symbols are permitted4 ,a feature useful both for ease of programming and for machine simulation is the ability to call for a series of instructions 7macro-instruction7 to be written4 ,frequently used instruction sequences thus need only to be defined once4 ,,decal - ,the ,compiler ,program ,,decal-#c 7,digital ,equipment ,compiler1 ,assembler1 and ,linking loader for ,,pdp-#c7 is an integrated programming system for ,,pdp-#c4 ,it incorporates in one system all of the essential features of advanced assemblers1 compilers1 and loaders4 ,,decal is both an assembler and compiler4 ,it combines the one-to-one translation facilities of an assembler1 and the one-to-many translation facilities of a formula translation compiler4 ,problem oriented language statements may be freely intermixed with symbolic machine language instructions4 ,a flexible loader is available to allow the specification of program location at load time4 ,the programmer may specify that certain variables and constants are systems variables and constants4 ,the symbols so defined are universally used in a system of many routines4 ,thus1 communications between parts of a major program is facilitated even though these parts may be compiled separately4 ,storage requirements for a large program are lessened by this technique4 ,,decal is an open-ended programming system and can be modified without a detailed understanding of the internal operation4 ,this is achieved by means of a recursive definition facility based on a skeleton compiler with a small set of logical capabilities4 ,the skeleton compiler acts as a bootstrap for introducing more sophisticated facilities4 ,the compiler will be delivered with a fully defined subset of formula translation operators4 ,additional subsets may be defined by the user to best fit his source language4 ,,floating ,,point ,,subroutines ,a set of subroutines are provided with the ,,pdp-#c to perform floating point arithmetic4 ,in these1 the ,,pdp-#c #cf bit word is divided to form a #bg bit mantissa1 a1 and #i bit exponent1 b4 ,numbers1 thus1 appear in the form3 k ax#b;b where1 a1 is considered to be in fractional form in the range #a_/b a #a1 and b is an integer1 #j b #bi4 ,this gives number1 k1 the range #aj-gf k #ajgf4 ,the subroutines are called with one operand in the accumulator4 ,after the subroutine has been executed1 the accumulator contains the answer4 ,thus floating point numbers are essentially handled as regular logical works4 ,the format of the number allows magnitude comparisons to be made by conventional arithmetic as bit #j is the sign of the number1 bits #a to #i the exponent1 and the remaining #bf bits1 together with the sign bit1 the mantissa in ones complement arithmetic4 ,the arithmetic subroutines are3 add1 subtract1 multiply1 divide1 convert a floating point number to binary1 convert a binary number to a floating number4 ,additional routines form3 square root of x1 ex1 ln x1 sine7pi_/#b7x1 cos7pi_/#b7x1 tan-#ax4 ,there are also programs to convert between floating decimal numbers and ,,pdp-#c floating numbers4 ,routines which require two operands1 e4g41 add1 subtract1 multiply and divide1 require an index register to specify the address of the second operand4 ,an index register also specifies parameters in data conversions1 e4g41 the position of the binary point when converting a binary number to a standard floating number4 ,using the floating point subroutines1 additional routines may be written which handle complex floating numbers and vector and matrix algebra4 ,,maintenance ,,routines ,maintenance ,routines are used exclusively to check the operation of the machine4 ,these routines are operated while varying the bias supply voltages1 and thus a check is made on possible degradation of all components which would affect the operation of the machine4 ,,miscellaneous ,,routines ,a variety of additional programs are provided with ,,pdp-#c4 ,one of the more important programs is the ,typewriter ,interrogator ,program 7,,tip74 ,,tip allows the typewriter to be used most effectively as an input-output link by which programs and data are examined and modified4 ,the features include request for printing of a series of registers1 interrogation and modification of the contents of registers1 and the ability to request new tapes after programs have been suitably modified4 ,communication is done completely via the typewriter in either octal numbers1 decimal numbers1 or alphanumeric codes4 ,register contents are presented in similar form4 ,other miscellaneous routines handle arithmetic processes1 e4g41 number conversions1 and communication with the input or output devices4 ,these routines include various format print outs1 paper tape and magnetic tape read in programs1 and display subroutines4 99 99 99 99 99 ,illustration3 ,,system ,,block ,,diagram ,,figure #a ,illustration3 ,,instruction ,,format ,,figure #b ,illustration3 ,,figure #c 99 99 99 99 99 ,transcriber's ,notes3 ,c 7,x7 and ,c7,x7 standardized to ,c7,x74 usec and usec4 standardized to usec4 throughout text4 ,other changes to the original text are listed below4 ,figure #d is referred to in the text1 but a copy could not be located4 ,underlined ,text is enclosed by underscores4 ,superscripts are marked with carats x#b and y-#c4 ,greek symbols are surrounded by tildes4 ,transcriber ,changes3 ,,table ,,of ,,contents3 ,originally ',operation' 7,operating ,speeds7 ,,table ,,of ,,contents3 ,originally ',frap' 7,,frap7 ,,table ,,of ,,contents3 ,originally ',routines' 7,subroutines7 ,page #d3 ,originally 'theoperate' 7while a program is operating by means of the operate instruction47 ,page #g3 ,added comma 7,the instruction base address1 ,y1 is in octal digits #g through #aa47 ,page #h3 ,standardized from 'sub-routines' 7,the conversion of decimal numbers into the binary system for use by the machine may be performed automatically by subroutines47 ,page #h3 ,standardized from 'sub-routine' 7the output conversion of binary numbers into decimals is done by subroutine47 ,page #af3 ,added comma 7,this instruction will shift the contents of the combined register right ,n positions1 where ,n is octal digits #g-aa of the instruction word47 ,page #af3 ,moved comma4 ,was 'left1 ,n positions' 7,this instruction will shift the contents of the combined registers left ,n positions1 where ,n is octal digits #g-aa of the instruction word47 ,page #ai3 ,was 'know' 7,most in-out operations require a known minimum time before completion47 ,page #bj3 ,removed inconsistent comma 7,these are the ,test ,address 7#ae bits71 the ,test ,word 7#cf bits71 and the ,sense ,switches 7#f bits747 ,page #ba3 ,changed comma to period 7the computer will halt at the completion of each memory cycle4 ,this switch is particularly useful in debugging programs47 ,page #bh3 ,was 'tpae' 7during reading or backspacing when the tape comes to an end of record gap47 ,page #bi3 ,standardized from 'de-select' 7the unit will deselect 7or disconnect747 ,page #ce3 ,was 'propares' 7,an assembler or compiler prepares a machine language tape suitable for direct interpretation7 ,page #ce3 ,removed comma 7,frequently used instruction sequences thus need only to be defined once47 ,page #cg3 ,was ',routiines' 7,routines which require two operands1 e4g41 add1 subtract1 multiply and divide7